In the field of image processing for displays, it is known to provide a so-called “display control unit” for receiving image data from a memory and converting the image data to signals for display by a visual display unit, for example a Liquid Crystal Display (LCD), such as a thin-film transistor (TFT) LCD.
The display control unit comprises a display controller for accessing the image data. The display controller typically also comprises a number of buffers into which the image data is transferred prior to processing by one or more functional unit, for example a pixel format converter. The image data is received in respect of a number of channels, each channel relating to a given “plane”. A so-called “blending unit” of the display controller therefore serves to combine the image data in respect of the different channels prior to display by the display unit driven by a display driver of the display control unit. In this regard, the image data is displayed at a predetermined update frequency, for example 60 Hz.
In order to fill the buffers, the image data is retrieved from a given memory by way of a memory access and stored in the buffers, different ranges of memory being used to stored image data respect of different channels. Whilst the buffers are being filled, the image data is being read out of buffers and processed and provided to the display at the predetermined frame rate. In contrast with the frequency at which signals are provided to the display unit, the image data read into the buffers is bandwidth limited as a result of limitations of the memory in which the image data is stored. In this respect, the memory may have priorities to serve other host units and so be unable to fill the buffers at a rate required by the display controller. Given that the display controller is unconcerned by the latency associated with operation of the memory from which the image data is obtained, it can be seen that circumstances can arise when one or more buffers lack image data for processing and driving the display unit. The display controller therefore continues to drive the display unit using empty buffers. This situation is known as an “underrun” condition and results in the display unit failing to display properly the image data intended for display.
US patent publication no. 2011/0169849 describes a graphics system including a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device. A buffer control circuit detects underruns of the buffer when the display controller is attempting to read pixel data from the buffer that has not yet been written to the buffer. In such circumstances, the buffer control circuit tried to ameliorate the situation by supplying a pixel to the display selected from a previously stored set of underrun pixels, for example a most recent valid pixel read by the display controller.
US patent publication no. 2010/0073388 also describes a display controller, but this document addresses the data feed latency by providing an alternative path to a Random Access Memory storing image data.
U.S. Pat. No. 7,843,460 describes a graphics processor that includes a memory for storing image data for presentation. The graphics controller also includes bandwidth control logic to monitor a data feed latency. When an underrun is detected, the graphics processor uses an averaging technique in order to average a given number of preceding pixels, or uses a previous pixel, in order to generate a final pixel for display.
US patent publication no. 2003/0142058 relates to an LCD controller architecture that employs a technique whereby pixels are tagged and discarded based upon whether the pixels are valid or invalid and pixels are not written to an output buffer in the event that an input buffer underruns.
US patent publication number 2003/0184532 relates to a display controller capable of automatically tuning an output rate thereof. The output rate of the display controller can be reduced by reducing a rate of a pixel clock or modifying image resolution.
In relation to all of the above described controllers, underruns are addressed either by techniques intended to avoid them or by techniques intended to mitigate the effects of the underruns. The above known controllers do not provide a useful level of diagnostic information.